Motor drive circuit with dischargeable capacitive network



970 J.'A. PARNELL 3,525,918

MOTOR DRIVE CIRCUIT WITH DISCHARGEABLE CAPACITIVE NETWORK Filed Nov. 1,1968 5Sheecs-Sheet l POS I TI ON TRANSDUCER SERVO MOTOR LIMIT 8 SLEWDETECTION SERVO AMP CIRCUIT I8 I FEEDBACK S I: N

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ATTORNEY Aug. 25, 1970 J. A. PARNELL MOTOR DRIVE CIRCUIT WITHDISGHARGEABLE CAPACITIVE NETWOaK Filed Nov. 1, 1968 5 Sheets-Sheet DON Wm: mm on n h v: j & a T r I .QN N ms I wv v mm .ll! I l l I l I I I IILm= JAMES A.

PARNELL INVENTQR.

ATTORNEY Aug. 25, 1970 J. A. PARNELL MOTOR DRIVE CIRCUIT WITHDISCHARGEABLE CAPACITIVE NETWORK 5 Sheets-Sheet 4 Filed Nov. 1, 1968JAMES A. PARNELL ATTORNEY w 25, 1970 J. A. PARNELL 3,525,918

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FIG. 5 WKM ATTORNEY United States Patent Ofliee 3,525,918 Patented Aug.25, 1970 3,525,918 MOTOR DRIVE CIRCUIT WITH DISCHARGEABLE CAPACITIVENETWORK James A. Parnell, Houston, Tex., assignor to Bausch &

Lomb Incorporated, Rochester, N.Y., a corporation of New York Filed Nov.1, 1968, Ser. No. 772,714 Int. Cl. G05b 5 01 US. Cl. 318-597 12 ClaimsABSTRACT OF THE DISCLOSURE A circuit is disclosed for driving a motorwith periodic current pulses that vary in duration. A response shapingcapacitive network is included in the forward loop of the drive circuit.A detection circuit monitors the duration of the current pulses todetermine when the motor is in a slew and/ or limit condition todischarge the capacitive network.

CROSS-REFERENCES TO RELATED APPLICATIONS A copending patent applicationSer. No. 773,398, filed Nov. 5, 1968, entitled Motor Drive Circuitincluding the circuitry disclosed in the present application was filedfor the inventor Wayne R. Isaacs and is assigned to the assignee of thepresent application. The copending patent application claims the motordrive and slew and/or limit detection system therefor.

BACKGROUND OF THE INVENTION This invention relates to servo systems ingeneral and more particularly to means for discharging capacitivenetworks in a servo system when in a slew and/or limit condition.

In most servo systems it is generally desirable to have as high afrequency response as possible so that the servo system can track acontrol system with a minimum amount of dynamic error. In order toachieve this rapid response, it is desirable to operate the servo motorat maximum power capacity to achieve maximum torque for acceleration,speed, etc. Furthermore, it is also desirable to have the open loop gainof the system as high as possible to reduce errors due to dead band,friction, etc., to an acceptable value. When incorporating such designrequirements in a closed loop system, stability becomes a problem,particularly when attempting to achieve an optimum frequency response.

In many servo systems tachometers are employed to generate a velocityfeedback signal that is used to stabilize the system at a higherfrequency response. Often tachometers are too expensive or for variousdesign or for other practical reasons cannot be included in the system.In such cases, networks are introduced in the servo system to shape theforward loop frequency response and phase shift characteristics so thatthe closed loop response can be extended with a suflicient margin ofstability.

In various servo systems, such as in recorders, etc., the range oftravel of the servo system is limited. Accordingly, some provisions mustbe included in the servo system to allow the servo to slew throughoutits range of travel and into the limit position at maximum speed, andthen stop and be held in the limit position until a signal is receivedto reverse the direction of travel. Once in the limit position, it ishighly desirable that the system will respond immediately to a reversesignal and move away from the limit position with a minmum of timedelay.

Generally, when servo systems are slewed or driven into a limitposition, the driving signal saturates a portion in the forward loop ofthe system resulting in non-linear operation. Any capacitive circuits,such as that used in lag or lead responsive shaping networks becomecharged to undesirably high levels. Before the system can berapidlyreversed from a slew condition, or be rapidly driven from thelimit position, the capacitive circuits must be discharged to allow thedrive signal to the motor to be reversed. The capacitors in suchnetworks are generally high in value and include relatively highimpedance discharge paths. If the capacitors are to be discharged by thesystem drive signals, an undesirable time delay is created until thecapacitors are discharged, resulting in a large error.

-It is therefore an object of this invention to provide a servo systemincluding a response shaping network in the forward loop and means forrapidly discharging the capacitive circuits when in a slew conditionand/or limit condition providing for rapid reversal.

SUMMARY OF THE INVENTION The circuit of the invention provides means forcontrolling the charge on a capacitive network in the forward loop of amotor drive circuit. It includes a pair of power control devices forapplying variable duration current pulses from an AC source to a motorto drive the motor in opposite directions and a control circuitresponsive to a signal from the capacitive network to control theconduction angle of the devices, when the motor drive circuit is in anon-linear mode of operation such as slew or limit conditions. Meansmeasure the conduction angle of the power control device to providecontrol signals when either of the devices exceed a preset conductionangle that terminates when the other device conducts. A switchingcircuit responsive to the control signals provides a low impedance pathacross the capacitive network.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified block diagramof a closed loop servo system including the invention.

FIG. 2 is a block diagram of a portion of the servo system of FIG. 1including the invention.

FIG. 3 is a schematic diagram of the drive circuit portion of the blockdiagram of FIG. 2.

FIG. 4 is a schematic diagram of the limit and slew circuitry portion ofthe block diagramof FIG. 2.

FIG. 5 is a graphic plot of the waveforms of the systems of FIGS. 1-4 toillustrate the operation of the system of FIGS. 14.

DESCRIPTION OF THE PREFERRED EMBODIMENT In the closed loop servo systemof FIG. 1, input drive signals are applied to a summing circuit 10 froman input circuit 11. The summing circuit 10 compares the input signal tothat derived from a feedback circuit 12 to apply a difference signalthrough a response shaping network 13 to a servo amplifier 14. The servoamplifier 14 applies the amplified difference signal to a servo motor 15which drives a load 16. A position transducer 17, coupled to the motor15, applies a positioned feedback signal to the feedback circuit 12. Themotor 15 is driven until the feedback signal cancels the input signal,resulting in a zero difference signal and a null position.

In the closed loop servo system of FIG. 1, the response shaping network13 was included in the forward loop of the system, to tailor the forwardloop frequency response. This allows the servo loop of the system to beclosed at a higher frequency to provide a better responding servo systemwith a suflicient degree of stability.

Response shaping networks generally comprises resistor-capacitor (R-C)circuits that are designed along with the input and output impedances ofthe intermediate stages to shape the frequency response of the system.The resistor and capacitor values are generally high and provide a longR-C time constant. This type of circuit functions well except when theservo system becomes satu rated by a large input signal. This oftenoccurs when the system receives a slew drive signal, or the load isdriven into a limit position. In such cases, the input circuit isgenerally saturated and the capacitors are charged to abnormal valuesdue to the non-linear mode of operation. The system cannot be reverseduntil the capacitors are discharged from this non-linear condition.Since the R-C time constant is long, this would require either a verylarge reverse error signal or a long time delay, neither of which iseither desirable or satisfactory.

The system of the invention includes a limit and'slew detection circuit18 that monitors the operation of'the servo amplifier 14 to determinewhen a slew or limit condition has been reached and prevents theresponse shaping network 13 from being charged to abnormal high valuesunder slew or limit conditions. Accordingly, the servo system can bereversed from either the slew or limit condition with a minimum of errorand time delay.

In FIG. 2 a servo motor 16 is illustrated as a split phase AC motorhaving a field winding 19 energized by an alternating signal 90 out ofphase from the signals applied to the motor control windings 20 and 21.An alternating current power source is to be connected between thecenter tap 22 and ground. A triac 23 (forward drive) and triac 24(reverse drive) are connected in series with the opposite ends of thecontrol windings 20 and 21, respectively. A triac is a semiconductorbi-directional triode switch that conducts with either polarity of an ACsignal applied thereto and requires an input pulse for each polarity orreversal of the AC power source. The triacs 23 and 24 are renderedconductive by control pulses from a forward pulse generator 25 andreverse pulse generator 26, respectively. The pulse generators 25 and 26generate a control pulse when the connected input capacitors 28 and 30,respectively, are charged to a predetermined voltage level.

The pulse generators are synchronized to the AC voltage by a one-shotmonostable flip-flop circuit 32. The

input circuit of the flip-flop circuit 32 is connected through a fullwave rectifying circuit 34 and receives a series of half wave 120 cyclepulses illustrated by the waveform 36 in FIG. 5. The flip-flop circuit32 is set on the negative going portion of the rectified pulse asdesignated by the dash line 38 and remains in the set" condition for atime duration sufiicient to extend into a portion of the next followinghalf cycle as illustrated by the waveform 40.

The capacitors 28 and 30 (FIG. 3) receive the square pulses 40 throughthe diodes 42 and 44 respectively. The capacitors 28 and 30 chargeduring the reset cycle of the flip-flop 32 to produce the saw-toothwaveforms 46 and 48 (FIG. 5). When the Waveforms 46 and 48 reach apredetermined voltage level 50 and 52, the connected pulse generatorgenerates the pulse signals 54 and 56 respectively, discharging thecapacitors 28 and 30 and rendering the triacs 23 and 24 conductive. Thisis a null idle type of condition wherein the motor is held stationary.Both triacs are conducting slightly as illustrated by the crosshatchedportions 58 to allow current flow simultaneously through both thewindings 20 and 21. The currents cancel each other but function tominimize dead band.

The rate at which the capacitors 28 and 30 charge is controlled by adilferential amplifier 60. The differential amplifier 60 is driven by adifferential amplifier 62 which in turn receives a single ended inputsignal from a frequency response shaping lag network 64. The inputsignals to the servo system are applied across the terminals 66 and areamplified by a preamplifier 68 which in turn drives the lag network 64.

When a direct current signal is applied to the terminals 66 the signalis amplified by amplifiers 68 and 62 and produces unbalanced output atthe differential amplifier 60. The unbalanced output causes thecapacitors 28 and 30 to charge at different rates. For example, if asignal having a polarity to produce forward rotation of the motor 16 isapplied to the terminal 66, the capacitor 28 charges at a substantiallygreater rate than the capacitor 30, as illustrated by the Waveforms 70and 72 of the FIG. 5. It should be noted that the first time thecapacitor 28 (waveform 70) is charged to the pulse level, a pulse 76 isgenerated (waveform 74) and the triac 23 is rendered conductive for theremainder of the half wave. In the particular example the triac 23 isrendered conductive at an angle of 90 of the rectified 60 cyclewaveform. The second pulse 78 does not effect the conduction of thetriac 23. The capacitor 30 charges at a very slow rate and does notreach the level to cause the pulse generator 26 to produce an outputpulse and is discharged each time the flip-flop 32 is set. When thetriac 23 conducts the motor 16 rotates in the forward direction.Although the triac is illustrated to be conductive for an angle of 90,it is to be understood, however, that the angle at which the triac isrendered conductive is varied depending upon the magnitude of the signalapplied to the terminal 66.

The limit circuit 18 functions to cut off the drive sig nal to the motorafter a period of time sufiicient to drive the motor into its limitposition. A second monostable one-shot flip-flop 80 is coupled to theflip-flop 32 to be set when the first flip-flop 32 is reset. The secondflip-flop 80 has a time duration in the set position that issubstantially shorter than the half cycle and is illustrated in FIG. 5as the waveform 82. The time duration of the flip-flop 82 is selected sothat it is reset at a conduction angle corresponding to the slewcondition of the motor and also a saturation condition of thepreamplifier 68, as designated by the dashed line 84.

The output from flip-flop 80 is connected to an input circuit of a pairof AND gate circuits 86 and 88. The other input circuit of the AND gatecircuits 86 and 88 are connected to receive pulses from the pulsegenerators 25 and 26 respectively. The output from the AND gate 86 isconnected to the set terminal of the forward latch flip-flop 90 whilethe output terminal of the AND gate 88 is connected to the set terminalof the reverse latch flip-flop 92. The output circuits of the flip-flopflops 90 and 92 are connected to the time delay switches 98 and 100. Thetime delay switches, when their time delay has run, are connected toshort the capacitors 28 and 30. This cuts oif any drive signal to themotor 16.

When the second flip-flop 80 is in the set condition, the occurrence ofa pulse from the connected pulse generator enables the AND gate and setsthe connected latch flip-flop. This condition is only possible when theamplifier 68 is saturated and the motor 16 is in the slew or limitcondition. This condition is illustrated by the dashed line 94 in FIG. 5extending between the pulse 76 (waveform 74) and the set condition offlip-flop -80 (waveform 82). When either flip-flop 90 or 92 are set theconnected time delay switch 98 or 100 respectively begins to time.

The curve 102 in FIG. 5 illustrates the latching action of the flip-flop90. A ramp signal is generated by the time delay switch 98 asillustrated by the curve 104. When the ramp reaches a predeterminedlevel 100 the time delay switch is actuated as illustrated by the curve108, to discharge the capacitor 28 and maintain the capacitor dischargedand the power to the motor cut off. The time duration of the delayswitches 98 and 100 is selected to be more than sufiicient to drive themotor into the limit position. The time delay begins to run when themotor has reached the slew condition or the motor has traveled to thelimit condition and the error signal becomes large enough to apply fullpower to the motor.

Without the limit and slew detection circuit, a capacitive component inthe lag network 64 would become charged to a high value when thepreamplifier 68 becomes saturated. If a change of direction signal isapplied to the terminal 66, the motor 16 would receive an impact signalwith a sufficient olfset signal until the capacitor in the network wassufliciently discharged. This causes an undersirable time delay whenchanging directions after a saturated condition. A switching circuit 112is connected to the lag network 64 to discharge the capacitive circuitwhen the preamplifier 68 reaches the saturated condition. The switchingcircuit 112 is connected to be actuated when either of the latchflip-flops 90 or 92 are set.

FIGS. 3 and 4 are detailed schematic diagrams illustrating componentswithin the blocks of FIG. 2. The blocks in FIG. 2 are designated inFIGS. 3 and 4 by dashed lines having the same reference numerals. Thepulse generator circuits 25 and 26 include a unijunction transistor 114connected as a relaxation oscillator time delay circuit to produce anoutput pulse when the connected capacitor reaches a preset level. Theoutput pulse from the unijunction transistor 114 which is coupled to thetriac reaches it through a transistor 116 connected in an emitterfollower circuit.

The differential amplifier 60 includes a pair of transistors 118, abalance potentiometer 120 and a motor current adjusting potentiometer122. The potentiometer 120 is set to balance the operation of the servosystem to a null condition. The potentiometer 122 is used to control theidle current flow through the motor in the null condition. Thetransistors 118 receive a double ended or balanced signal from thedifferential amplifier 62.

The differential amplifier 62 includes a pair of transistors 124 andpotentiometer 126 that functions as a gain control. The difierentialamplifier 62 has a non-linear gain characteristic that somewhatcompensates for the nonlinear gain characteristics of the current versusconduction angle of the triacs to provide a more linear operation.

The input to the differential amplifier 62 is single ended and isdeveloped across the lag network 64. The lag network includes tworesistors 131 and 128 and a capacitor 132 connected in a series. Inputsignals from the preamplifier 68 are applied through the resistor 131 tothe amplifier 62. A field effect transistor 134 is connected across thecapacitor 132 and the resistor 131 (as the switch 112, FIG. 2) forshorting the voltage across the capacitor to ground when receiving aswitching signal on the terminal 136.

The full wave rectifier circuit 34 includes a pair of diodes 138 and 140for full wave rectification of the voltage applied to the terminals 141and 144. The 120 cycle signal from the diodes is coupled to the one-shotflip-flop 32, through a current limiting resistor 145, which includesthe transistors 146, 148, and 150. The output from the oneshot flip-flop32 is coupled through the diodes 42 and 44 to the bases of unijunctiontransistors 114 and the collectors of the transistors 118. The one-shotflip-flop 32, the amplifier 62, and the pulse generating circuits 25 and26 are conventionally energized by a direct current potential applied tothe connected terminals 119 and 121 with the designated polarity.

As previously mentioned, the one-shot flip-flop 32 produces a 120 cyclesquare wave as illustrated by the waveform 40. The capacitors 28 and 30are charged during the reset portion of the cycle as illustrated by thecurves 46 and 48. When the unijunctions 114 fire they discharge theconnected capacitor and generate the pulses illustrated by the curves54, 56, and 74 to fire the connected triacs, 23 and 24.

In FIG. 4 the output from the one-shot flip-flop 32 is applied to theterminal 160 and coupled through a capacitor 162 and a diode 164 to setthe flip-flop 80'. The flipflop 80 includes the transistors 166, 168,and 170 connected as a monostable flip-flop circuit.

The diodes 172 and 174 form the AND gate 86 while the diodes 176 and 178form the AND gate 88. The output from the flip-flop is applied to thediodes 172 and 176. The latch flip-flops and 92 include a pair oftransistors 180 and 182 connected as bi-sta-ble flip-flop circuits. Theoutputs from the flip-flops 90 and 92 are connected to the terminal 136through the resistors 192 and 194. The terminal 136 (FIG. 3) isconnected to the switching field effect transistor 134. When either ofthe flip-flops or 192 are set, a switch signal is applied to theterminal 136 to discharge the capacitor 132. This condition occurs whenthe servo system is in the slew condition and/ or limit condition.

The pulses from the forward pulse generator 25 are applied to a terminal200 while the pulses from the reverse pulse generator 26 are applied tothe terminal 202. Pulses on the terminals 200 and 202 are appliedthrough the diodes 203 and 201 to reset the flip-flops 92 and 90respectively and also to the AND gates diodes 178 and 174.

The time delay switch circuits 98 and 100 include a unijunctiontransistor 204 driven by an emitter follower transistor 206. When theconnected flip-flop is set, an energizing potential is applied to thetransistor 206 at the same time the capacitor 208 is charged. The R-Ctime constant of the resistor 210 and the capacitor 208 is sufiicient toprovide the required time delay, which can be, for example, one second.When the voltage across the capacitor 208 reaches the predeterminedlevel 106 (FIG. 5 the unijunction 204 is rendered conductive andsaturates the connected transistor 212.

The transistor 212 is connected through the resistor 214 to a terminal216, or 218, which in FIG. 2 are connected to the capacitors 28 and 30.When a unijunction 204 is rendered conductive, the transistor 212eifectively shorts the connected capacitor in the pulse generatingcircuit and cuts off this drive signal to the motor. The unijunctiontransistor 204 remains in the conductive state since it is driven by alow impedance emitter follower transistor 206 until the connectedflip-flop circuit is reset. The connected flip-flop is reset by areverse signal applied to one of the terminals 200 and 202.

According to the foregoing, the limit delay switches 98 and 100 begin totime as soon as the motor 16 receives sufiicient power to designate aslew or limit condition. The slew condition is determined if a pulsefrom either of the pulse generators 25 and 26 occurs during the time thesecond one-shot flip-flop 80 is set. At this time, the correspondinglatch flip-flop 90 or 92 is set and the connected time delay switch 98or 100 begins to run. If a reverse signal is received before the time onthe time delay switch has run, the circuits are all reset to a normaloperating mode. On the other hand, if the time delay switch has runthrough its delay period, the motor is now in the limit condition andthe power is removed from the drive circuit. Hence, in one mode ofoperation, the time delay switch begins to run when a slew signal isfirst applied to the motor.

On the other hand, if the motor 16 is slowly driven to its limit oftravel, the time delay switch will not run until the input signal is ofsufficient amplitude so that the timing of the driving signal (frompulse generator 25 or 26) with reference to the operation of flip-flop88 corresponds to the slew condition. At this time, the flip-flop 90 or92 will be latched and the time delay of the switches 98 and 100 beginsto run. Hence, in this mode of operation the power will be cut oil whenthe motor has reached its limit position and the input signal is ofsufiicient amplitude to correspond to the power for slew.

In either mode of operation, the point at which the slew power conditionis preset is determined by the power capabilities of the motor. The gainof the preamplifier can now be selected so that when the slew conditionis achieved (maximum desirable motor velocity and/or acceleration) thepreamplifier 68 approaches a saturated condition thereby using the fullcapabilities of the preamplifier. The switch 112 for the lag network 64minimizes problems in the system due to saturation as previously setforth.

I claim:

1. A motor drive circuit comprising:

a motor;

a pair of terminals for connection to an AC power source;

first and second control devices each having first and second terminalsdefining a controllable current path therebetween and a control terminalfor controlling current conduction between said first and secondterminals;

circuit means for connecting said first control device to said motor andsaid pair of terminals for driving said motor in a first direction;

circuit means for connecting said second control device to said motorand said pair of terminals for driving said motor in a second direction;

an input circuit for receiving a direct current motor control signal;

a network including a capacitive ele'ment coupled to receive said motorcontrol signal from said input circuit;

a first phase sensitive control circuit synchronized to said powersource coupled to said control terminal of said first device forgenerating a drive signal for rendering said device conductive for aportion of a cycle of the AC power;

a second phase sensitive control circuit synchronized to said powersource coupled to said control terminal of said second device forgenerating a drive signal for rendering said device conductive for aportion of a cycle of the AC power;

circuit means connecting said first and second control circuits to saidnetwork so that a change in the magnitude of said motor control signalin one direction from a reference level increases the conduction angleof said first device and a change in the opposite direction increasesthe conduction of said second device;

comparison circuit means for comparing the occurrence of a drive signalwith the phase angle of the AC power source to generate a switchingsignal when a preset conduction angle has been reached; and

circuit means coupled between said comparison circuit means and saidnetwork for applying a low impedance discharge path across saidcapacitive element when said switching signal is generated.

2. A motor drive circuit comprising:

a motor;

a pair of terminals for connection to an AC power source;

first and second control devices connected to said motor and said ACpower source for driving said motor in opposite directions with variableduration current pulses at a rate synchronized to said AC power source;

an input circuit for receiving a direct current motor control signal;

a resistance-capacitance network coupled to receive control signals fromsaid input circuit;

a control circuit coupled between said network and said first and secondcontrol device and synchronized to said power source for increasing theduration of the pulses from said first device when the control signalfrom the network changes in a first direction from a reference level andfor increasing the duration of pulses from said second device when thesignal changes in an opposite direction from said reference level;

circuit means for determining the duration of said current pulses andgenerating a switching signal when the pulses exceed a predeterminedduration; and

switching means coupled between said circuit means and said network forproviding a low impedance discharge path in response to said switchingsignal.

3. A motor drive circuit comprising:

input circuit means, including a capacitive network,

for receiving a direct current motor control signal;

a motor; i

a pair of terminals for connection to an AC power source; first andsecond power control means connected between said pair of terminals andsaid motor for applying variable duration current pulses from saidsource to said motor so that said first and second power control meansdrive said motor in opposite directions;

first control circuit means connected to said first power control meansand said input circuit means for controlling the duration of saidcurrent pulses as a function of the sense and magnitude of said motorcontrol signal relative to a reference potential to drive said motor ina first direction;

second control circuit means connected to said second power controlmeans and said input circuit means for controlling the duration of saidcurrent pulses as a function of the sense and magnitude of said motorcontrol signal relative to said reference potential to drive the motorin a second direction opposite said first direction;

circuit means coupled to said first and second power control means formeasuring the time duration of the variable duration current pulses andfor providing a switching signal when the duration of one 'of thecurrent pulses reaches a preset time duration corresponding to powerrequired for the motor to slew; and

switching means coupled between said capacitive network and said circuitmeans responsive to said switching signal for switching a low impedancepath across said capacitive network.

4. A motor drive circuit as defined in claim 3 wherein:

said circuit means includes a first detection circuit coupled to saidfirst power control means for providing a first switching signal whenthe time duration of said current pulses exceeds said preset timeduration wherein the first switching signal continues until said secondpower means conducts, and a second detection circuit coupled to saidsecond power control means for providing a second switching signal whenthe time duration of said current pulses exceed said preset timeduration wherein the first switching signal continues until said firstpower means conducts; and

said switching means is responsive to said first and second switchingsignals to switch said low impedance path across said capacitivenetwork. 5. In a motor drive circuit including first and second powerdevices for applying variable duration rectified AC pulses to a motorfrom an AC power source for driving said motor in opposite directionsand a control circuit responsive to a motor control signal from an inputcircuit including a capacitive network for controlling conduction of thepower devices and the duration of the pulses as of function of theamplitude and sense of the motor control signal, the improvementcomprising: first circuit means synchronized to said AC power source forproviding at least one reference signal for each cycle said referencesignal having a preset time duration shorter than the period of a cycle;

first and second bistable switching circuits having first and secondstable modes of operation;

second circuit means coupled to said first and second bistable switchingcircuits for switching said first switching circuit into the first modeof operation when said second power device is rendered conductive andfor switching said second switching circuit into the first mode ofoperation when said first power device is rendered conductive;

third circuit means coupled to said first switching circuit forswitching said first switching circuit to the second mode of operationwhen the first power device is conductive during said reference signalindicating sufficient power for motor slew in a first direction; j

fourth circuit means coupled to said second switching circuit forswitching said second switching'circuit to the second mode of operationwhen said second power device is conductive during said reference signalindicating sutficient power for motor slew in a second direction; and

a switching circuit coupled between the capacitive network and saidfirst and second bistable switching circuits for switching a lowimpedance pathi across said capacitive network when one of said firstand second bistable switching circuits are in saidsecond mode ofoperation. 6. The improvement as defined in claim wherein said firstcircuit means provides a reference signal for each half cycle of said ACpower source and has a time duration of less than a half cycle. 7. In amotor drive circuit including first and second power control means forapplying variable duration rectified AC pulses from an AC power sourceto a motor for driving said motor in opposite directions and a controlcircuit responsive to a motor control signal from an inputcircuitincluding a capacitive network for con trolling the conduction of thepower control means and the duration of the pulses as a function of theamplitude and sense of the motor control signal, the improvementcomprising:

first circuit means coupled to said first and second power control meansfor measuring the conduction angle of said first power control means andfor providing a first continuous control signal when a preset conductionangle is exceeded, said first control signal being continuous until saidsecond power control means conducts;

second circuit means coupled to said first and second power controlmeans for measuring the conduction angle of said second power controlmeans and for providing a second continuous control signal when a presetconduction angle is exceeded, said second control signal beingcontinuous until said first power control means conducts; and

switching means coupled between said capacitive network and said firstand second circuit means responsive to said first and second controlsignals to switch a low impedance path across at least a portion of saidcapacitive network to reduce the charge on said network while at leastone of said .first and second control signals are preset.

8. In a motor drive circuit including first and second power controlmeans for applying variable duration rectified AC pulses from an ACpower source for driving a motor in opposite directions along a pathhaving two limits of travel and a control signal responsive to theamplitude and sense of a motor control signal from an input circuitincluding a resistor-capacitor network for inversely controlling theconduction angle of the first and second power control means, theimprovement comprising:

first circuit means synchronized to said AC power source for providingat least one reference signal for each cycle having a first preset timeduration shorter than the period of a cycle defining a preset conductionangle corresponding to power designation for motor slew;

second circuit means coupled to said first and second power controlmeans and said first control means for comparing the conduction angle ofsaid, first power control means with said reference signal to preset afirst control signal when the conduction angle of said first powercontrol means exceeds said preset conduction angle, which first controlsignal is terminated by the conduction of said second power controlmeans;

third circuit means coupled to said first and second power control meansand said first circuit means for comparing the conduction angle of saidsecond power control means with said reference signal to provide asecond control signal when the conduction angle exceeds said presetconduction angle, which second control signal is terminated by theconduction. of said first po'yver control means; and

a switching circuit coupled between said resistor-capacitor network andsaid second and third circuit means responsive to one of said first andsecond control signals for switching a low impedance path to saidnetwork for controlling .the charge in said network.

9. The improvement as defined in claim 8 wherein said first circuitmeans provides a reference signal for each half cyclelof said AC powersource initiated at approximately the beginning of each half cycle andextending for a time duration less than a half cycle.

10. The improvement as defined in claim 8 wherein:

said second circuit means includes a bistable circuit that is switchedinto a first mode of operation to generate said first control signalwhen the first power control means conducts during the presence of saidreference signal and; is switched into a second mode of operation whensaid second power control means conducts; and i said third circuit meansincludes a bistable circuit that is switched into a first mode ofoperation to generate said second control signal when the second powercontrol means conducts during the presence of said reference signal andis switched into a second mode of operation when said first powercontrol means conducts.

11. The improvement as defined in claim 8 including:

time delay circuit means coupled between said second and third circuitmeans and said control circuit for inactivating said first power controlmeans in response to the first control signal when the duration of saidfirst control signal exceeds a second preset time duration and forinactivating said second power control means in response to said secondcontrol signal when the duration of said second control signal exceedssaid second preset time duration, wherein said second preset time delayis sufficient to at least slew said motor between said two limitpositions; and

said switching circuit maintains said low impedance path as long as saidtime delay circuit means inactivates one of said first and second powercontrol means.

12. A motor drive circuit comprising:

a motor;

first and second control devices each having first and second terminalsexhibiting a controllable current path therebetween and a controlterminal for rendering each of said devices conductive;

a pair of terminals for connection to a source of alternating currentpower;

first circuit means connecting said first and second terminals of firstand second devices between said pair of terminals and said motor fordriving said motor in opposite directions;

an input circuit including an amplifier for receiving a motor controlsignal;

a resistor-capacitor response shaping network coupled to receiveamplified motor control signals from said input circuit;

a first control circuit coupled to said pair of terminals and thecontrol terminal of said first device for applying control signalsthereto synchronized to said source for controlling the conduction angleof said device;

a second control circuit coupled to said pair of terminals and thecontrol terminal of said second device for applying control signalsthereto synchronized to said source for controlling the conduction angleof said device;

second circuit means connecting said network to said first and secondcontrol circuits for increasing the conduction angle of said firstdevice and decreasing the conduction angle of said second device whenthe input signal changes in a first direction with respect to areference potential and decreasing the conduction angle of said firstdevice and increasing the conduction angle of said second device whenthe input signal changes in a second direction;

third circuit means coupled to said pair of terminals for providing atleast one geference signal for each cycle of the source voltage having apreset time duration substantially less than the period of a cycle;

first and second bistable switching means, each having first and secondstable modes of operation;

fourth circuit means connecting said first and second bistable switchingmeans to said second and first control circuits, respectively, forswitching said first and second switching means into said first mode ofoperation by said control signals;

fifth circuit means coupling said first bistable switching means to saidfirst control circuit and said third circuit means for switching intosaid second mode of operation when said control signal is generatedduring said reference signal;

sixth circuit means coupling said second bistable switching means tosaid second control circuit and said third circuit means for switchinginto said second mode of operation when said control signal is generatedduring said reference signal; and

switching means coupled between said network said first-and secondbistable switching means for providing a low impedance path to saidnetwork for reducing the charge on said network while one of said firstand second bistable switching means are in said second mode ofoperation.

References Cited UNITED STATES PATENTS 3,378,739 4/1968 Livengood et a1.3 18-48 3,403,310 9/1968 Davidoff 318l8 3,430,117 2/1969 Sennhenn 318-28XR BENJAMIN DOBECK, Primary Examiner US. Cl. X.R. 3 18626, 286

